This invention relates to a nonvolatile semiconductor memory device and a technique of manufacturing the same. More particularly, the invention relates to a technique effective for improving a manufacturing yield and reliability of a nonvolatile semiconductor memory device.
A flash memory, which is a semiconductor nonvolatile memory, has been widely used as a data storage memory of good portability.
The memory array systems of a flash memory typically include a NAND type wherein memory cells are connected in series and an AND type wherein memory cells are connected in parallel. Especially, the latter makes use of a hot electron writing method, thus ensuring high-speed writing. Additionally, the memory array arrangement is in parallel connection, not in series connection like the NAND type, and thus, has the feature that it is unlikely to suffer an influence of memory information of other cells.
The AND flash memory is disclosed, for example, in Japanese Unexamined Patent Publication No. 2001-156275. The memory cell set out in this publication has a selective transistor element provided with a switch gate electrode on a semiconductor substrate, a memory cell transistor element that includes a gate insulating film discretely having traps at opposite sides thereof and a memory gate electrode, and a diffusion layer formed at the outside thereof and connected to a source line/bit line.
Japanese Unexamined Patent Publication No. 2001-28428 discloses an AND flash memory of a virtual ground type wherein a memory cell is constituted of n-type semiconductor regions (source, drain) formed in a p-type well of a semiconductor substrate and three gates.